74 search results - page 1 / 15 » Built-in test generation for synchronous sequential circuits |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...
VTS
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
CORR
2011
Springer
12 years 12 months ago
2011
Springer
This paper investigates the impact of the changes of the characteristic polynomials and initial loadings, on behaviour of aliasing errors of parallel signature analyzer (Multi-Inp...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is...
ATS
1996
IEEE
13 years 9 months ago
1996
IEEE
A hierarchical test generation method is presented that uses the inherent hierarchical structure of the circuit under test and takes fault diagnosability into account right from t...