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» CAD challenges for 3D ICs
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ASPDAC
2009
ACM
160views Hardware» more  ASPDAC 2009»
13 years 8 months ago
CAD challenges for 3D ICs
David S. Kung, Ruchir Puri
31
Voted
DAC
2011
ACM
12 years 4 months ago
Thermal-aware cell and through-silicon-via co-placement for 3D ICs
Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductiv...
Jason Cong, Guojie Luo, Yiyu Shi
SLIP
2009
ACM
13 years 11 months ago
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
ISQED
2007
IEEE
236views Hardware» more  ISQED 2007»
13 years 11 months ago
3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method
Due to the roaring power dissipation and gaining popularity of 3D integration, thermal dissipation has been a critical concern of modern VLSI design. The availability for chip-lev...
Dongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu
VRML
2003
ACM
13 years 9 months ago
3D virtual clothing: from garment design to web3d visualization and simulation
One of the major challenges in Computer Graphics concerns the 3D representation and physically-based simulation of garments. In our research, we are working closely with the texti...
Luca Chittaro, Demis Corvaglia