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» CAD challenges for 3D ICs
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ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
13 years 3 months ago
Pre-bond testable low-power clock tree design for 3D stacked ICs
Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with prebond testability because designers can avoid stack...
Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K...
ICCAD
2005
IEEE
118views Hardware» more  ICCAD 2005»
14 years 3 months ago
Thermal via planning for 3-D ICs
Heat dissipation is one of the most serious challenges in 3D IC designs. One effective way of reducing circuit temperature is to introduce thermal through-the-silicon (TTS) vias....
Jason Cong, Yan Zhang
GLVLSI
2006
IEEE
165views VLSI» more  GLVLSI 2006»
14 years 5 days ago
Block alignment in 3D floorplan using layered TCG
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S...
DATE
2009
IEEE
183views Hardware» more  DATE 2009»
14 years 26 days ago
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on C...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
CVPR
2011
IEEE
12 years 9 months ago
Effective 3D Object Detection and Regression Using Probabilistic Segmentation Features in CT Images
3D object detection and importance regression/ranking are at the core for semantically interpreting 3D medical images of computer aided diagnosis (CAD). In this paper, we propose ...
Le Lu, Jinbo Bi, Matthias Wolf, Marcos Salganicoff