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» CMOS gate modeling based on equivalent inverter
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FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
13 years 10 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
ICCAD
1997
IEEE
99views Hardware» more  ICCAD 1997»
13 years 9 months ago
High-level area and power estimation for VLSI circuits
High-level power estimation, when given only a high-level design specification such as a functional or RTL description, requires high-level estimation of the circuit average acti...
Mahadevamurty Nemani, Farid N. Najm
ASPDAC
2010
ACM
165views Hardware» more  ASPDAC 2010»
13 years 2 months ago
Dynamic power estimation for deep submicron circuits with process variation
- Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow...
Quang Dinh, Deming Chen, Martin D. F. Wong
ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
13 years 10 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
EUROCRYPT
2010
Springer
13 years 9 months ago
Protecting Circuits from Leakage: the Computationally-Bounded and Noisy Cases
Abstract. Physical computational devices leak side-channel information that may, and often does, reveal secret internal states. We present a general transformation that compiles an...
Sebastian Faust, Tal Rabin, Leonid Reyzin, Eran Tr...