Modern FPGAs, such as the Xilinx Virtex-II Series, offer the feature of partial and dynamic reconfiguration, allowing to load various hardware configurations (i.e., HW modules) du...
In this paper, we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict topdown Hardware/So...
Klaus Buchenrieder, Andreas Pyttel, Alexander Sedl...
We propose a new method for defragmenting the module layout of a reconfigurable device, enabled by a novel approach for dealing with communication needs between relocated modules ...
A new paradigm to support the communication among modules dynamically placed on a reconfigurable device at runtime is presented. Based on the network on chip (NoC) infrastructure...
Christophe Bobda, Ali Ahmadinia, Mateusz Majer, J&...
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...