55 search results - page 3 / 11 » Caches and Hash Trees for Efficient Memory Integrity |
ACSAC
2006
IEEE
13 years 9 months ago
2006
IEEE
Several secure computing hardware architectures using memory encryption and memory integrity checkers have been proposed during the past few years to provide applications with a t...
DAC
2003
ACM
13 years 10 months ago
2003
ACM
The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved perfo...
CF
2006
ACM
13 years 9 months ago
2006
ACM
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
IPPS
1998
IEEE
13 years 9 months ago
1998
IEEE
In this paper, we present ScalParC (Scalable Parallel Classifier), a new parallel formulation of a decision tree based classification process. Like other state-of-the-art decision...
ISCA
2010
IEEE
13 years 7 months ago
2010
IEEE
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...