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» Caching processor general registers
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ICS
2001
Tsinghua U.
13 years 9 months ago
Integrating superscalar processor components to implement register caching
A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a l...
Matt Postiff, David Greene, Steven E. Raasch, Trev...
LCTRTS
2007
Springer
13 years 11 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
GLVLSI
2007
IEEE
162views VLSI» more  GLVLSI 2007»
13 years 9 months ago
Utilizing custom registers in application-specific instruction set processors for register spills elimination
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
Hai Lin, Yunsi Fei
ISCA
2011
IEEE
522views Hardware» more  ISCA 2011»
12 years 9 months ago
CPPC: correctable parity protected cache
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...
Mehrtash Manoochehri, Murali Annavaram, Michel Dub...
CIKM
2009
Springer
13 years 12 months ago
Location cache for web queries
This paper proposes a strategy to reduce the amount of hardware involved in the solution of search engine queries. It proposes using a secondary compact cache that keeps minimal i...
Mauricio Marín, Flavio Ferrarotti, Marcelo ...