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ICCD
2004
IEEE
135views Hardware» more  ICCD 2004»
14 years 2 months ago
Design Methodologies and Architecture Solutions for High-Performance Interconnects
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...
Davide Pandini, Cristiano Forzan, Livio Baldi
DAC
2000
ACM
13 years 9 months ago
TACO: timing analysis with coupling
: The impact of coupling capacitance on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach...
Ravishankar Arunachalam, Karthik Rajagopal, Lawren...
ISPD
1998
ACM
88views Hardware» more  ISPD 1998»
13 years 9 months ago
An efficient technique for device and interconnect optimization in deep submicron designs
In this paper, we formulate a new class of optimization problem, named the general CH-posynomial program, and reveal the general dominance property. We propose an efcient algorith...
Jason Cong, Lei He
EOR
2000
102views more  EOR 2000»
13 years 5 months ago
Multiple center capacitated arc routing problems: A tabu search algorithm using capacitated trees
In the capacitated arc routing problem with multiple centers (M-CARP) the objective is to
Anita Amberg, Wolfgang Domschke, Stefan Voß
COR
2006
93views more  COR 2006»
13 years 5 months ago
Solving capacitated arc routing problems using a transformation to the CVRP
A well known transformation by Pearn, Assad and Golden reduces a Capacitated Arc Routing Problem (CARP) into an equivalent Capacitated Vehicle Routing Problem (CVRP). However, tha...
Humberto Longo, Marcus Poggi de Aragão, Edu...