366 search results - page 1 / 74 » Circuit optimization using statistical static timing analysi... |
DAC
2005
ACM
13 years 6 months ago
2005
ACM
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is dif...
ISPD
2000
ACM
13 years 9 months ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for hig...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...