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CODES
2008
IEEE
13 years 7 months ago
Specification-based compaction of directed tests for functional validation of pipelined processors
Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...
Heon-Mo Koo, Prabhat Mishra
VLSID
2007
IEEE
160views VLSI» more  VLSID 2007»
14 years 5 months ago
Spectral RTL Test Generation for Microprocessors
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...
Nitin Yogi, Vishwani D. Agrawal
DATE
2000
IEEE
139views Hardware» more  DATE 2000»
13 years 9 months ago
A VHDL Error Simulator for Functional Test Generation
This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. Al...
Alessandro Fin, Franco Fummi
ITC
1995
IEEE
104views Hardware» more  ITC 1995»
13 years 8 months ago
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
Nur A. Touba, Edward J. McCluskey
ICANNGA
2007
Springer
161views Algorithms» more  ICANNGA 2007»
13 years 9 months ago
Evolutionary Induction of Decision Trees for Misclassification Cost Minimization
Abstract. In the paper, a new method of decision tree learning for costsensitive classification is presented. In contrast to the traditional greedy top-down inducer in the proposed...
Marek Kretowski, Marek Grzes