90 search results - page 3 / 18 » Clock distribution using multiple voltages |
ISCAS
2008
IEEE
14 years 5 days ago
2008
IEEE
—A simple low-area and low-power clock frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. In this circuit, 2n voltage controlled delay lines (...
ISVLSI
2008
IEEE
14 years 5 days ago
2008
IEEE
Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large cap...
ISLPED
2004
ACM
13 years 11 months ago
2004
ACM
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by dee...
ICCD
2003
IEEE
14 years 2 months ago
2003
IEEE
— We model the power fluctuation as cycle-to-cycle power gradient and minimize the mean of the power gradients using ILP. We propose scheduling schemes for three modes of datapa...
ICCD
2001
IEEE
14 years 2 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...