27 search results - page 2 / 6 » Code-coverage Based Test Vector Generation for SystemC Desig... |
TVLSI
2008
13 years 4 months ago
2008
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
GLVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
There has been considerable research on quantum dots cellular automata as a new computing scheme in the nano-scale regimes. The basic logic element of this technology is a majorit...
IFIP
2001
Springer
13 years 9 months ago
2001
Springer
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
DDECS
2006
IEEE
13 years 11 months ago
2006
IEEE
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...