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» Collection and Analysis of Microprocessor Design Errors
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AND
2009
13 years 3 months ago
Tools for monitoring, visualizing, and refining collections of noisy documents
Developing better systems for document image analysis requires understanding errors, their sources, and their effects. The interactions between various processing steps are comple...
Daniel P. Lopresti, George Nagy
DAC
2003
ACM
14 years 6 months ago
Using a formal specification and a model checker to monitor and direct simulation
We describe a technique for verifying that a hardware design correctly implements a protocol-level formal specification. Simulation steps are translated to protocol state transiti...
Serdar Tasiran, Yuan Yu, Brannon Batson
ISLPED
1995
ACM
116views Hardware» more  ISLPED 1995»
13 years 8 months ago
Activity-sensitive architectural power analysis for the control path
Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criteria. As such there is a growing ...
Paul E. Landman, Jan M. Rabaey
ISCA
2007
IEEE
120views Hardware» more  ISCA 2007»
13 years 11 months ago
Examining ACE analysis reliability estimates using fault-injection
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel
DAC
2005
ACM
14 years 6 months ago
StressTest: an automatic approach to test generation via activity monitors
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
Ilya Wagner, Valeria Bertacco, Todd M. Austin