14007 search results - page 2 / 2802 » Communications in Bus Networks |
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
CODES
2006
IEEE
13 years 11 months ago
2006
IEEE
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
IEEEARES
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper investigates fault effects and error propagation in a FlexRay-based network with hybrid topology that includes a bus subnetwork and a star subnetwork. The investigation...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
Abstract— A split shared-bus architecture with multiple simultaneous bus accesses is proposed. Compared to traditional bus architectures, the performance of proposed architecture...
SLIP
2006
ACM
13 years 11 months ago
2006
ACM
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...