15 search results - page 1 / 3 » Compact CLEFIA Implementation on FPGAS |
FPL
2011
Springer
12 years 4 months ago
2011
Springer
In this paper two compact hardware structures for the computation of the CLEFIA encryption algorithm are presented. One structure based on the existing state of the art and a nove...
CHES
2003
Springer
13 years 10 months ago
2003
Springer
Abstract. In this paper a compact FPGA architecture for the AES algorithm with 128-bit key targeted for low-cost embedded applications is presented. Encryption, decryption and key ...
RECONFIG
2008
IEEE
13 years 11 months ago
2008
IEEE
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
ASAP
2010
IEEE
13 years 2 months ago
2010
IEEE
Abstract--This paper proposes an FPGA-based applicationspecific elliptic curve processor over a prime field. This research targets applications for which compactness is more import...
GLVLSI
2009
IEEE
2009
IEEE
Physical unclonable function and true random number generator: a compact and scalable implementation
13 years 8 months ago
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...