Sciweavers

15 search results - page 2 / 3
» Compact CLEFIA Implementation on FPGAS
Sort
View
CEE
2007
105views more  CEE 2007»
13 years 5 months ago
Compact modular exponentiation accelerator for modern FPGA devices
We present a compact FPGA implementation of a modular exponentiation accelerator suited for cryptographic applications. The implementation efficiently exploits the properties of m...
Timo Alho, Panu Hämäläinen, Marko H...
FPL
2006
Springer
161views Hardware» more  FPL 2006»
13 years 9 months ago
Predictive Load Balancing for Interconnected FPGAs
A Field Programmable Gate Array (FPGA), when used as a platform for implementing special-purpose computing architectures, offers the potential for increased functional parallelism...
Jason D. Bakos, Charles L. Cathey, Allen Michalski
DAC
1995
ACM
13 years 9 months ago
Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs
In this paper we present a set cover based approach (SCP) to multi-way partitioning for minimum delay for Look-Up Table based FPGAs. SCP minimizes the number of chip-crossings on ...
Prashant Sawkar, Donald E. Thomas
ERSA
2006
129views Hardware» more  ERSA 2006»
13 years 7 months ago
Group-Alignment based Accurate Floating-Point Summation on FPGAs
Floating-point summation is one of the most important operations in scientific/numerical computing applications and also a basic subroutine (SUM) in BLAS (Basic Linear Algebra Sub...
Chuan He, Guan Qin, Mi Lu, Wei Zhao
FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
13 years 9 months ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi