7 search results - page 1 / 2 » Compact Test Generation Using a Frozen Clock Testing Strateg... |
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
JISE
2000
13 years 4 months ago
2000
TVLSI
2008
13 years 4 months ago
2008
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
WEA
2005
Springer
13 years 10 months ago
2005
Springer
Abstract. A5/1 pseudo-random bit generator, known from GSM networks, potentially might be used for different purposes, such as secret hiding during cryptographic hardware testing, ...