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ITNG
2007
IEEE
13 years 11 months ago
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
SIES
2008
IEEE
13 years 11 months ago
Performance evaluation of a java chip-multiprocessor
—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-m...
Christof Pitter, Martin Schoeberl
EUROSYS
2007
ACM
14 years 2 months ago
Comparing the performance of web server architectures
In this paper, we extensively tune and then compare the performance of web servers based on three different server architectures. The µserver utilizes an event-driven architectur...
David Pariag, Tim Brecht, Ashif S. Harji, Peter A....
CMG
2000
13 years 6 months ago
Comparing CPU Performance Between and Within Processor Families
Our study compares CPU performance on RISC and CISC uni and multiprocessors of varying speeds, and shows that the Instruction Set Architecture (ISA) style no longer matters. Our s...
Lee A. Butler, Travis Atkison, Ethan L. Miller
IEEEPACT
2006
IEEE
13 years 11 months ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi