Sciweavers

18 search results - page 4 / 4
» Compilation of imperative synchronous programs with refined ...
Sort
View
POPL
1995
ACM
13 years 8 months ago
Default Timed Concurrent Constraint Programming
d Abstract) We extend the model of [VRV94] to express strong time-outs (and pre-emption): if an event A does not happen through time t, cause event B to happen at time t. Such con...
Vijay A. Saraswat, Radha Jagadeesan, Vineet Gupta
DAC
1997
ACM
13 years 9 months ago
A C-Based RTL Design Verification Methodology for Complex Microprocessor
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon ...
CODES
2008
IEEE
13 years 6 months ago
Performance debugging of Esterel specifications
Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based...
Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samar...