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MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 4 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
MMB
2012
Springer
259views Communications» more  MMB 2012»
12 years 1 months ago
Boosting Design Space Explorations with Existing or Automatically Learned Knowledge
Abstract. During development, processor architectures can be tuned and configured by many different parameters. For benchmarking, automatic design space explorations (DSEs) with h...
Ralf Jahr, Horia Calborean, Lucian Vintan, Theo Un...
ICRA
2003
IEEE
184views Robotics» more  ICRA 2003»
13 years 11 months ago
Trajectory planning for smooth transition of a biped robot
- This paper presents a third-order spline interpolation based trajectory planning method which is aiming to achieve smooth biped swing leg trajectory by reducing the instant veloc...
Zhe Tang, Changjiu Zhou, Zengqi Sun
ISCA
2007
IEEE
110views Hardware» more  ISCA 2007»
14 years 1 days ago
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities an...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
13 years 11 months ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh