24 search results - page 3 / 5 » Compositional, dynamic cache management for embedded chip mu... |
CODES
2002
IEEE
13 years 10 months ago
2002
IEEE
The aggressive evolution of the semiconductor industry — smaller process geometries, higher densities, and greater chip complexity — has provided design engineers the means to...
IEEEPACT
2008
IEEE
14 years 5 days ago
2008
IEEE
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
ISCA
2009
IEEE
14 years 12 days ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
HPCA
2011
IEEE
12 years 9 months ago
2011
IEEE
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilizatio...
ICS
2005
Tsinghua U.
13 years 11 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...