5 search results - page 1 / 1 » Comprehensive Evaluation of an Instruction Reissue Mechanism |
ISPAN
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper, we evaluate a mechanism to reissue instructions on the mispredicted speculation path. An instruction which is once dispatched to a functional unit during mispredict...
ISCAPDCS
2001
13 years 6 months ago
2001
In this paper, we propose a fault-tolerant mechanism for microprocessors, which detects transient faults and recovers from them. There are two driving force to investigate fault-t...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
DSN
2008
IEEE
13 years 11 months ago
2008
IEEE
The last few years have witnessed an unprecedented explosion in transistor densities. Diminutive feature sizes have enabled microprocessor designers to break the billion-transisto...
DSN
2005
IEEE
13 years 11 months ago
2005
IEEE
The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avo...