16 search results - page 2 / 4 » Concurrent Specification and Timing Analysis of Digital Hard... |
CASES
2008
ACM
13 years 7 months ago
2008
ACM
Detailed or cycle-accurate/bit-accurate (CABA) simulation is a critical phase in the design flow of embedded systems. However, with increasing system complexity, full detailed sim...
CASES
2005
ACM
13 years 7 months ago
2005
ACM
The concurrent synchronous language Esterel allows proto treat reactive systems in an abstract, concise manner. An Esterel program is typically first translated into other, non-s...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software ? e.g., into sequent...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
ASAP
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper presents a technique to map automatically a complete digital signal processing (DSP) application onto a parallel machine with distributed memory. Unlike other applicati...