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MICRO
2005
IEEE
108views Hardware» more  MICRO 2005»
13 years 11 months ago
How to Fake 1000 Registers
Large numbers of logical registers can improve performance by allowing fast access to multiple subroutine contexts (register windows) and multiple thread contexts (multithreading)...
David W. Oehmke, Nathan L. Binkert, Trevor N. Mudg...
PPOPP
2009
ACM
14 years 5 months ago
Comparability graph coloring for optimizing utilization of stream register files in stream processors
A stream processor executes an application that has been decomposed into a sequence of kernels that operate on streams of data elements. During the execution of a kernel, all stre...
Xuejun Yang, Li Wang, Jingling Xue, Yu Deng, Ying ...
ISCA
2003
IEEE
124views Hardware» more  ISCA 2003»
13 years 10 months ago
Banked Multiported Register Files for High-Frequency Superscalar Microprocessors
Multiported register files are a critical component of high-performance superscalar microprocessors. Conventional multiported structures can consume significant power and die ar...
Jessica H. Tseng, Krste Asanovic
CASES
2006
ACM
13 years 11 months ago
Adapting compilation techniques to enhance the packing of instructions into registers
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
Stephen Hines, David B. Whalley, Gary S. Tyson
ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
13 years 8 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang