141 search results - page 2 / 29 » Core Algorithms of the Maui Scheduler |
IPPS
2010
IEEE
13 years 2 months ago
2010
IEEE
Multi-core organizations increasingly support multiple threads per core. Threads on a core usually share a single first-level data cache, so thread schedulers must try to minimize ...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
SIPS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, we investigate the efficient software implementations of the Montgomery modular multiplication algorithm on a multi-core system. A HW/SW co-design technique is use...
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
FAST
2008
2008
Enhancing Storage System Availability on Multi-Core Architectures with Recovery-Conscious Scheduling
13 years 5 months ago
In this paper we develop a recovery conscious framework for multi-core architectures and a suite of techniques for improving the resiliency and recovery efficiency of highly conc...