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IEEEPACT
2006
IEEE
13 years 11 months ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
DSN
2008
IEEE
13 years 11 months ago
Scheduling algorithms for unpredictably heterogeneous CMP architectures
In future large-scale multi-core microprocessors, hard errors and process variations will create dynamic heterogeneity, causing performance and power characteristics to differ amo...
Jonathan A. Winter, David H. Albonesi
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
13 years 6 months ago
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures
Abstract-- We address performance maximization of independent task sets under energy constraint on chip multi-processor (CMP) architectures that support multiple voltage/frequency ...
Sushu Zhang, Karam S. Chatha
IEEEPACT
2008
IEEE
13 years 11 months ago
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aa...
ICCD
2008
IEEE
159views Hardware» more  ICCD 2008»
14 years 1 months ago
Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor
— Heterogeneous Chip Multiprocessors (HMPs), such as the Cell Broadband Engine, offer a new design optimization opportunity by allowing designers to provide accelerators for appl...
Michael Gschwind