45 search results - page 1 / 9 » Cost Effective Implementation of Asynchronous Two-Level Logi... |
WCE
2007
13 years 5 months ago
2007
- We proposed the cost effective (in sense of gate number) asynchronous two-level logic. It is based on AND-OR implementation of minimized logic functions. We formulated and proved...
ISCA
1998
IEEE
13 years 8 months ago
1998
IEEE
As the issue rate and depth of pipelining of high performance Superscalar processors increase, the importance of an excellent branch predictor becomes more vital to delivering the...
DDECS
2009
IEEE
13 years 11 months ago
2009
IEEE
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....
COMPCON
1994
IEEE
13 years 8 months ago
1994
IEEE
A fully asynchronous implementation of the ARM microprocessor has been developed in order to investigate the potential of asynchronous logic for low-power applications. The work d...
ASPLOS
1998
ACM
13 years 8 months ago
1998
ACM
This paper describes the Network-Attached Secure Disk (NASD) storage architecture, prototype implementations of NASD drives, array management for our architecture, and three files...