52 search results - page 2 / 11 » Cost and Benefit Models for Logic and Memory BIST |
VLSID
2005
IEEE
13 years 10 months ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Abstract—Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may...
IEEEPACT
1998
IEEE
13 years 9 months ago
1998
IEEE
Software fine-grain distributed shared memory (FGDSM) provides a simplified shared-memory programming interface with minimal or no hardware support. Originally software FGDSMs tar...
WCET
2008
13 years 6 months ago
2008
WCET analysis models for superscalar out-of-order CPUs generally need to be pessimistic in order to account for a wide range of possible dynamic behavior. CPU hardware modificatio...
ATS
2009
IEEE
13 years 10 months ago
2009
IEEE
Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-fre...