Sciweavers

27 search results - page 2 / 6
» Cost-free scan: a low-overhead scan path design
Sort
View
ITC
2003
IEEE
170views Hardware» more  ITC 2003»
13 years 10 months ago
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zha...
ATS
1996
IEEE
93views Hardware» more  ATS 1996»
13 years 8 months ago
Testable Design and Testing of MCMs Based on Multifrequency Scan
In this paper, we present a novel and efticient approach to test MCM at the module as well as chip levels. Our design incorporates the concept of the multifrequency test method an...
Wang-Dauh Tseng, Kuochen Wang
DAC
1996
ACM
13 years 8 months ago
Test Point Insertion: Scan Paths through Combinational Logic
We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses th...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...
DATE
2006
IEEE
109views Hardware» more  DATE 2006»
13 years 10 months ago
A secure scan design methodology
It has been proven that scan path is a potent hazard for secure chips. Scan based attacks have been recently demonstrated against DES or AES and several solutions have been presen...
David Hély, Frédéric Bancel, ...
TCAD
1998
125views more  TCAD 1998»
13 years 4 months ago
Test-point insertion: scan paths through functional logic
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...