54 search results - page 2 / 11 » Coverage Metrics for Formal Verification |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
UML
2004
Springer
13 years 10 months ago
2004
Springer
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
—In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining faultinjection in high level design (HLD) descriptions with a forma...
ASPDAC
2006
ACM
13 years 8 months ago
2006
ACM
CONCUR
2006
Springer
13 years 8 months ago
2006
Springer
One of the advantages of temporal-logic model-checking tools is their ability to accompany a negative answer to the correctness query by a counterexample to the satisfaction of the...