Sciweavers

58 search results - page 1 / 12
» Critical path analysis using a dynamically bounded delay mod...
Sort
View
VTS
2007
IEEE
95views Hardware» more  VTS 2007»
13 years 11 months ago
Delay Test Quality Evaluation Using Bounded Gate Delays
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...
Soumitra Bose, Vishwani D. Agrawal
ITC
2000
IEEE
88views Hardware» more  ITC 2000»
13 years 9 months ago
Predicting device performance from pass/fail transient signal analysis data
Transient Signal Analysis (TSA) is a Go/No-Go device testing method that is based on the analysis of voltage transients at multiple test points. In this paper, a technique based o...
James F. Plusquellic, Amy Germida, Jonathan Hudson...
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
14 years 1 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic
IFM
2009
Springer
124views Formal Methods» more  IFM 2009»
13 years 11 months ago
Dynamic Path Reduction for Software Model Checking
We present the new technique of dynamic path reduction (DPR), which allows one to prune redundant paths from the state space of a program under verification. DPR is a very general...
Zijiang Yang, Bashar Al-Rawi, Karem Sakallah, Xiao...