58 search results - page 2 / 12 » Critical path analysis using a dynamically bounded delay mod... |
ISCAS
2003
IEEE
13 years 11 months ago
2003
IEEE
We present an equation-based transistor size optimizer that minimizes delay of custom circuits. Our method uses static timing analysis to find the critical paths and numerical met...
FOCS
1997
IEEE
13 years 9 months ago
1997
IEEE
A central issue in the design of modern communication networks is that of providing performance guarantees. This issue is particularly important if the networks support real-time t...
TVLSI
2008
13 years 5 months ago
2008
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...