46 search results - page 2 / 10 » Crosstalk analysis in nanometer technologies |
VLSID
2004
IEEE
14 years 6 months ago
2004
IEEE
With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of r...
SOCC
2008
IEEE
14 years 13 days ago
2008
IEEE
— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra...
CODES
2006
IEEE
14 years 4 days ago
2006
IEEE
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
TVLSI
2008
13 years 6 months ago
2008
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
INTEGRATION
2008
13 years 6 months ago
2008
Variation is a significant concern in nanometer-scale CMOS due to manufacturing equipment being pushed to fundamental limits, particularly in lithography. In this paper, we review...