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» Custom Hardware Architectures for Posture Analysis
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ISCAS
2006
IEEE
146views Hardware» more  ISCAS 2006»
13 years 11 months ago
XML-based customization along the scalability axes of H.264/AVC scalable video coding
Abstract— The heterogeneity in the current and future multimedia environment requires an elegant adaptation framework for the production and consumption of different kinds of mul...
Davy De Schrijver, Wesley De Neve, Koen De Wolf, S...
ICECCS
2009
IEEE
166views Hardware» more  ICECCS 2009»
13 years 3 months ago
ASIIST: Application Specific I/O Integration Support Tool for Real-Time Bus Architecture Designs
In hard real-time systems such as avionics, computer board level designs are typically customized to meet specific reliability and real time requirements. This paper focuses on co...
Min-Young Nam, Rodolfo Pellizzoni, Lui Sha, Richar...
ICCD
2004
IEEE
122views Hardware» more  ICCD 2004»
14 years 2 months ago
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity fo...
Krishnan Srinivasan, Karam S. Chatha, Goran Konjev...
ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
13 years 12 months ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...
WMPI
2004
ACM
13 years 11 months ago
A low cost, multithreaded processing-in-memory system
This paper discusses die cost vs. performance tradeoffs for a PIM system that could serve as the memory system of a host processor. For an increase of less than twice the cost of ...
Jay B. Brockman, Shyamkumar Thoziyoor, Shannon K. ...