Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures

Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents novel linear programming based techniques for synthesis of custom NoC architectures. In the nanoscale regime, low power consumption would continue to be an important design goal. We first discuss an optimal mixed integer linear programming (MILP) formulation that synthesizes a low power NoC architecture subject to the performance constraints. The MILP formulation is limited by large run times. We next present heuristic techniques that exploit clustering, and 0-1 constraint relaxation to reduce the run times of the formulation. The techniques minimize power as the primary goal, and minimize the number of routers (area) as a secondary goal. We p...

• Type: Conference
• Year: 2004
• Where: ICCD
• Authors: Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
• Keywords: Custom Noc Architectures, Hardware, ICCD 2004, Low Power Noc, Techniques Minimize Power