4 search results - page 1 / 1 » Cycle error correction in asynchronous clock modeling for cy... |
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
— As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficien...
DSN
2005
IEEE
13 years 10 months ago
2005
IEEE
Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop er...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
IPPS
2006
IEEE
13 years 10 months ago
2006
IEEE
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...