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2006
IEEE
13 years 11 months ago
A bus architecture for crosstalk elimination in high performance processor design
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increas...
Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang
CGO
2005
IEEE
13 years 11 months ago
Performance of Runtime Optimization on BLAST
Optimization of a real world application BLAST is used to demonstrate the limitations of static and profile-guided optimizations and to highlight the potential of runtime optimiz...
Abhinav Das, Jiwei Lu, Howard Chen, Jinpyo Kim, Pe...
MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 4 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
TKDE
2002
140views more  TKDE 2002»
13 years 5 months ago
Transaction Processing in Mobile, Heterogeneous Database Systems
As technological advances are made in software and hardware, the feasibility of accessing information "any time, anywhere" is becoming a reality. Furthermore, the diversi...
James B. Lim, Ali R. Hurson
CGO
2004
IEEE
13 years 9 months ago
Static Identification of Delinquent Loads
The effective use of processor caches is crucial to the performance of applications. It has been shown that cache misses are not evenly distributed throughout a program. In applic...
Vlad-Mihai Panait, Amit Sasturkar, Weng-Fai Wong