36 search results - page 2 / 8 » Data Reuse Analysis Technique for Software-Controlled Memory... |
ISSS
2000
IEEE
13 years 9 months ago
2000
IEEE
Efficient use of an optimized custom memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption i...
ICPP
2002
IEEE
13 years 10 months ago
2002
IEEE
Recently, several experimental studies have been conducted on block data layout as a data transformation technique used in conjunction with tiling to improve cache performance. In...
ISPASS
2008
IEEE
13 years 11 months ago
2008
IEEE
—The potential for improving the performance of data-intensive scientific programs by enhancing data reuse in cache is substantial because CPUs are significantly faster than me...
VLSISP
2008
13 years 3 months ago
2008
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
ISCA
1997
IEEE
13 years 9 months ago
1997
IEEE
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...