69 search results - page 4 / 14 » Datapath Synthesis for Standard-Cell Design |
DAC
2005
ACM
13 years 7 months ago
2005
ACM
We investigate differences in power between application-specific integrated circuits (ASICs) and custom integrated circuits, with examples from 0.6um to 0.13um CMOS. A variety of ...
ICCD
2003
IEEE
14 years 2 months ago
2003
IEEE
— We model the power fluctuation as cycle-to-cycle power gradient and minimize the mean of the power gradients using ILP. We propose scheduling schemes for three modes of datapa...
ASPDAC
1995
ACM
13 years 9 months ago
1995
ACM
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
: Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes are adopted to reduce...
ICCAD
2007
IEEE
2007
IEEE
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
13 years 9 months ago
Abstract: Polynomial computations over fixed-size bitvectors are found in many practical datapath designs. For efficient RTL synthesis, it is important to identify good decompositi...