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» Decoding-Aware Compression of FPGA Bitstreams
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TVLSI
2011
265views more  TVLSI 2011»
12 years 11 months ago
Decoding-Aware Compression of FPGA Bitstreams
Abstract—Bitstream compression is important in reconfigurable system design since it reduces the bitstream size and the memory requirement. It also improves the communication ba...
Xiaoke Qin, Chetan Muthry, Prabhat Mishra
FPL
2008
Springer
207views Hardware» more  FPL 2008»
13 years 6 months ago
Bitstream compression techniques for Virtex 4 FPGAs
This paper examines the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardwa...
Radu Stefan, Sorin Dan Cotofana
FCCM
2000
IEEE
148views VLSI» more  FCCM 2000»
13 years 9 months ago
An Adaptive Cryptographic Engine for IPSec Architectures
Architectures that implement the Internet Protocol Security (IPSec) standard have to meet the enormous computing demands of cryptographic algorithms. In addition, IPSec architectu...
Andreas Dandalis, Viktor K. Prasanna, José ...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
13 years 11 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...