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ASPDAC
2008
ACM
92views Hardware» more  ASPDAC 2008»
13 years 6 months ago
Decomposition based approach for synthesis of multi-level threshold logic circuits
Scaling is currently the most popular technique used to improve performance metrics of CMOS circuits. This cannot go on forever because the properties that are responsible for the ...
Tejaswi Gowda, Sarma B. K. Vrudhula
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
13 years 8 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
14 years 5 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal
DATE
2010
IEEE
175views Hardware» more  DATE 2010»
13 years 8 months ago
Approximate logic synthesis for error tolerant applications
─ Error tolerance formally captures the notion that – for a wide variety of applications including audio, video, graphics, and wireless communications – a defective chip that...
Doochul Shin, Sandeep K. Gupta
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
13 years 10 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier