Sciweavers

46 search results - page 2 / 10
» Decoupling capacitance allocation for timing with statistica...
Sort
View
ICCD
2001
IEEE
213views Hardware» more  ICCD 2001»
14 years 2 months ago
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2GHz has caused crosstalk noise to become a serious problem, that degr...
Payam Heydari, Massoud Pedram
ASPDAC
2006
ACM
137views Hardware» more  ASPDAC 2006»
13 years 11 months ago
Parameterized block-based non-gaussian statistical gate timing analysis
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
DATE
2006
IEEE
129views Hardware» more  DATE 2006»
13 years 11 months ago
Non-gaussian statistical interconnect timing analysis
This paper focuses on statistical interconnect timing analysis in a parameterized block-based statistical static timing analysis tool. In particular, a new framework for performin...
Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
DAC
2008
ACM
14 years 6 months ago
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
S. Raja, F. Varadi, Murat R. Becer, Joao Geada
TCAD
2010
98views more  TCAD 2010»
12 years 12 months ago
Statistical Modeling With the PSP MOSFET Model
PSP and the backward propagation of variance (BPV) method are used to characterize the statistical variations of metal-oxide-semiconductor field effect transistors (MOSFETs). BPV s...
Xin Li, Colin C. McAndrew, Weimin Wu, Samir Chaudh...