The timing models used in current Static Timing Analysis tools use gate delays only for single input switching events. It is well known that the temporal proximity of signals arriv...
Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraha...
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
The engineering of computer vision systems that meet application speci c computational and accuracy requirements is crucial to the deployment of real-life computer vision systems....
Michael Greiffenhagen, Visvanathan Ramesh, Dorin C...