9 search results - page 1 / 2 » Deep Submicron Interconnect Timing Model with Quadratic Rand... |
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Shrinking feature sizes and process variations are of increasing concern in modern technology. It is urgent that we develop statistical interconnect timing models which are harmon...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
— The inductance and coupling effects in interconnects and non-linear receiver loads has resulted in complex input signals and output loads for gates in the modern deep submicron...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...