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VLSID
2007
IEEE
160views VLSI» more  VLSID 2007»
14 years 5 months ago
Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques
Claas Cornelius, Frank Grassert, Siegmar Koppe, Di...
ISCAS
1999
IEEE
110views Hardware» more  ISCAS 1999»
13 years 9 months ago
Noise-tolerant dynamic circuit design
-- Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency o...
Lei Wang, Naresh R. Shanbhag
ASPDAC
2005
ACM
97views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Opportunities and challenges for better than worst-case design
The progressive trend of fabrication technologies towards the nanometer regime has created a number of new physical design challenges for computer architects. Design complexity, u...
Todd M. Austin, Valeria Bertacco, David Blaauw, Tr...
IOLTS
2006
IEEE
103views Hardware» more  IOLTS 2006»
13 years 11 months ago
Designing Robust Checkers in the Presence of Massive Timing Errors
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
Frederic Worm, Patrick Thiran, Paolo Ienne
ISQED
2007
IEEE
197views Hardware» more  ISQED 2007»
13 years 11 months ago
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
The deep submicron (DSM) semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions sho...
Toshinori Sato, Yuji Kunitake