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» Defect tolerance for nanocomputer architecture
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SLIP
2004
ACM
13 years 10 months ago
Defect tolerance for nanocomputer architecture
Arvind Kumar, Sandip Tiwari
FCCM
2006
IEEE
106views VLSI» more  FCCM 2006»
13 years 11 months ago
Defect-Tolerant Nanocomputing Using Bloom Filters
We propose a novel defect-tolerant design methodology using Bloom filters for defect mapping for nanoscale computing devices. It is a general approach that can be used for any pe...
Gang Wang, Wenrui Gong, Ryan Kastner
ICPR
2004
IEEE
14 years 6 months ago
From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers
Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regula...
Jie Han, Pieter Jonker
FPL
2005
Springer
112views Hardware» more  FPL 2005»
13 years 10 months ago
Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
Anthony J. Yu, Guy G. Lemieux
DFT
2004
IEEE
134views VLSI» more  DFT 2004»
13 years 9 months ago
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars
Defect tolerance is an extremely important aspect in nano-scale electronics as the bottom-up selfassembly fabrication process results in a significantly higher defect density comp...
Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lomb...