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» Defect-tolerant Logic with Nanoscale Crossbar Circuits
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TCAD
2008
115views more  TCAD 2008»
13 years 4 months ago
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories
Abstract--The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) deco...
M. Haykel Ben Jamaa, Kirsten E. Moselund, David At...
ICCAD
2007
IEEE
92views Hardware» more  ICCAD 2007»
14 years 1 months ago
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we sug...
M. Haykel Ben Jamaa, Kirsten E. Moselund, David At...
ET
2007
123views more  ET 2007»
13 years 4 months ago
Defect-tolerant Logic with Nanoscale Crossbar Circuits
Crossbar architectures are one approach to molecular electronic circuits for memory and logic applications. However, currently feasible manufacturing technologies introduce numero...
Tad Hogg, Greg Snider
ISMVL
2008
IEEE
134views Hardware» more  ISMVL 2008»
13 years 11 months ago
Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells
Nanoscale multiple-valued logic systems require the development of nanometer scale integrated circuits and components. Due to limits in device physics, new components must be deve...
Theodore W. Manikas, Dale Teeters
FPGA
2006
ACM
141views FPGA» more  FPGA 2006»
13 years 8 months ago
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
Dmitri B. Strukov, Konstantin Likharev