7 search results - page 1 / 2 » Delay and Area Efficient First-level Cache Soft Error Detect... |
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
—Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but ar...
ISCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...
MICRO
2007
IEEE
13 years 11 months ago
2007
IEEE
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
SC
2009
ACM
13 years 11 months ago
2009
ACM
We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of addin...
ISQED
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...