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» Deriving a simulation input generator and a coverage metric ...
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DAC
2002
ACM
11 years 3 months ago
Deriving a simulation input generator and a coverage metric from a formal specification
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
Kanna Shimizu, David L. Dill
ICCD
2001
IEEE
119views Hardware» more  ICCD 2001»
10 years 11 months ago
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
We present a simulation-based semi-formal veriļ¬cation method for sequential circuits described at the registertransfer level. The method consists of an iterative loop where cove...
Serdar Tasiran, Farzan Fallah, David G. Chinnery, ...
CODES
2004
IEEE
10 years 6 months ago
System-on-chip validation using UML and CWL
In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design...
Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo...
UM
2001
Springer
10 years 7 months ago
Modeling Literary Style for Semi-automatic Generation of Poetry
Abstract. The generation of formal poetry involves both complex creativity usually exercised by a human poet - and strict algorithmic restrictions regarding the metrical structure ...
Pablo Gervás
UML
2004
Springer
10 years 8 months ago
System-on-Chip Verification Process Using UML
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro...
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