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EVOW
1999
Springer
13 years 10 months ago
Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms
This paper describes a new approximate approach for checking the correctness of the implementation of a protocol interface, comparing its lowlevel implementation with its high-leve...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
ICCD
2007
IEEE
206views Hardware» more  ICCD 2007»
14 years 3 months ago
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
Julian J. H. Pontes, Rafael Soares, Ewerson Carval...
TVLSI
2008
140views more  TVLSI 2008»
13 years 6 months ago
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
Jorge Campos, Hussain Al-Asaad
DAC
2000
ACM
13 years 10 months ago
Using general-purpose programming languages for FPGA design
ct General-purpose programming languages (GPL) are effective vehicles for FPGA design because they are easy to use, extensible, widely available, and can be used to describe both t...
Brad L. Hutchings, Brent E. Nelson
IPPS
2005
IEEE
13 years 12 months ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna